Pipelined Cordic Based Cascade Orthogonal IIRDigital

Cordic based cascade orthogonal IIR digital lters possess desirable properties for VLSI implementations such as local connection, regularity, absence of limit cycle and overrow oscillations, and good nite word-length behavior. However, the achievable sample rate of these lters is limited, since these structures can't be pipelined at ner levels (such as bit or multi-bit level) due to the presence of feedback loops. In this paper, we present a novel approach to design pipelined Cordic based cascade orthogonal IIR digital lters using the transfer function approach. We rst present a systematic way to synthesize cascade orthogonal IIR digital lters using scalar lossless inverse scattering theory, and realize the lter transfer function as a cascade inter-connection of orthogonal sections where each section implements one real zero or a pair of complex conjugate zeroes of the transfer function. In this way, the lter achieves low sensitivity over the entire lter spectrum. Novel pipelining techniques for both coarse-grain and ne-grain pipelining of these lters are then proposed. In coarse-grain pipelining, we present a novel method based on retiming and orthogonal matrix decomposition techniques which can increase the maximum lter sample rate to O(1) level which is independent of the lter order. In ne-grain pipelining, we present a novel method based on constraint lter design and polyphase decomposition techniques which could increase the maximum lter sample rate to any desired level. The proposed architecture for coarse-grain pipelining consists of only Givens rotations, and the one for ne-grain pipelining consists of only Givens rotations and a few additions. Both architectures can be realized using Cordic arithmetic based processors. Finally, nite word-length simulations are carried out to compare the performance of diierent topologies.